RE: Make, make, make. . .

[Erik <br0ke@math.smsu.edu>]

On 12-Apr-2000 Ishpeck wrote:
> Where might I find a good resource for documentation on wrighting
> makefiles?  I don't know jack diddly about Make (having come from a
> DOS/Borland world where we have projects instead of makefiles).
> 

makefiles are very simple. :) There is plenty of good documentation at
www.gnu.org/manuals/, as well as in your info and man documentation (try typing
info make, or info info if you haven't used info before... gnome-help-browser
gives you a nice GUI for info where you can navigate much like a web browser.
The two important things you want to know are variables and rules. Variables
are declared like this

        BLAH = something

and the variable is accessed like $(BLAH). They are useful for putting
information in a single place so it can be easily modified, instead of hunting
down and editing information several places in a makefile.

The really important stuff is in the rules. Rules are defined with a target,
dependancies, and an action. The format is like this

target: dependancies
        action

The target either a special name, like "all" or "install", or the name of the
finished component that the rule is responsible for making. Note that the only
real pertinance to order is the first rule is the default rule. So if you want
'all' to be the default rule, put all: before the other rules. There are more
advanced tricks like recursive makefiles (for multiple directory projects), and
shell executions, and stuff, but those should be left for later. A typical
basic makefile for a C program might look like this

helloworld: helloworld.o
        gcc -o helloworld helloworld.o
helloworld.o: helloworld.c
        gcc -c helloworld.c
clean:
        rm -f helloworld helloworld.o core

There are 3 rules defined, and no variables. Note that the clean rule has no
dependancies, and that the helloworld program has a dependancy on an object
generated by another rule. If you play around with makefiles of that format,
you should have a good feeling for the rule system. There are some other tricks
that can be very useful for slightly larger programs, the following is a
slightly more complex makefile. The .c.o target is a special target for make,
if a .o file is requested to be built, it will attempt to built that object
using the .c file with the same name (so graphics.o will attempt to use
graphics.c)

# this line is a makefile comment
OBJECTS = main.o keyboard.o graphics.o sound.o physics.o
TARGET = mygame
LIBS = -lX11 -lXext -lGL -lesound

$(TARGET): $(OBJECTS)
        gcc -o $(TARGET) $(OBJECTS) $(LIBS)
.c.o:
        gcc -c $<
clean:
        rm -f $(TARGET) $(OBJECTS) *~ core

If you want to get into more complex makefile environments, I strongly suggest
learning automake and autoconf instead. :) Hope this helps

        -Erik <erik@smluc.org> [http://math.smsu.edu/~br0ke]

The opinions expressed by me are not necessarily opinions. In all
probability, they are random rambling, and to be ignored. Failure to ignore
may result in severe boredom or confusion. Shake well before opening. Keep
Refrigerated.
        

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